(1) Field of the Invention
The invention relates to SRAM memory cells and, more particularly, to a method to improve soft error rate immunity in a SRAM cell through the novel addition of storage capacitance.
(2) Description of the Prior Art
Static RAM, or SRAM, devices are used in many electronic design applications. SRAM devices provide read/write capability with relatively low current consumption compared to dynamic RAM (DRAM). In deep submicron technology, the SRAM is very popular due to its advantages of high speed and lower power consumption. Therefore, SRAM is frequently used in communications and system on chip (SOC) products.
Design approaches to further reduce SRAM cell size and power consumption and to improve thermal stability have been ongoing in the art. This is particularly true due to the increasing size of SRAM arrays on integrated circuit devices. To achieve smaller cell size and to reduce power consumption, designers have developed SRAM devices that operate on reduced voltage supplies.
Referring now to FIG. 1, a conventional SRAM memory cell 10 is illustrated. This SRAM cell 10 comprises six transistors and is called a 6T cell. The 6T cell comprises a bi-stable flip-flop that, in turn, comprises transistors PU1 34, PD1 38, PU2 42, and PD2 46. In this arrangement, a first inverter is formed by the first pull-up PU1 34 and the first pull-down PD1 38. A second inverter is formed by the second pull-up PU2 42 and the second pull-down PD2 46. Note that the inverters are chained together, input to output, to form storage nodes ST1 58 and ST2 62. This is called a bi-stable flip-flop because the inverters can maintain either of two, stable conditions. In the first condition, ST1 58 is low (VSS) and ST2 62 is high (VCC). In the second condition, ST1 58 is high and ST2 62 is low. The feedback of each inverter output to the other inverter input makes the flip-flop stable in either state once the state is initialized.
Access transistors PG1 50 and PG2 54 provide a means to read or write data to the flip-flop. The access transistors PG1 50 and PG2 54 are controlled by word line signals WL 30. It is common for the SRAM cells 10 to be arrayed in columns and rows and for a row of cells to be commonly selected using a single word line WL 30 signal. The bit line BL 26 and bit line bar BLB 22 signals are used for reading or writing the cell 10. For example, during a write operation, the BL signal is forced to the desired write data state while the BLB signal is forced to the opposite state. When WL is then asserted, the new state (BL) is forced into the cell. When WL is then de-asserted, the cell 10 will maintain the new state on the storage node ST1 58 and the bar state on storage node ST2 62.
A significant measure of SRAM cell performance is the ability of the cell 10 to maintain the data state in the presence of various types of noise and soft error factors. For example, the cell 10 must maintain a written state in the presence of noise on the VCC 14 line.
The above-described work to reduce the cell 10 size typically means that the individual transistors are made smaller. As is typical in the art, this also may mean that the gate oxides are made thinner and the source/drain junctions are made shallower. These approaches allow the formation of smaller and faster switching transistors. However, such design changes also require that supply voltage VCC 14 be reduced to insure the reliability of these devices. As discussed above, the reduction of the supply voltage VCC 14 can have a positive additional effect of reducing the power consumption of the SRPM device given by P=I×V.
While the above-described changes can be good for the SRAM performance, they are not derived without cost. In particular, the reduction in power supply VCC 14 voltage can make the resulting SRAM cell 10 more susceptible to soft error rate effects. Soft error rate is a measure of the ability of the cell 10 to maintain a data state in the presence of environmental noise such as alpha (α) particles. Alpha particles are a form of radiation energy commonly found in the environment. Alpha particles are very high energy particles that are very capable of penetrating many objects in the environment.
Referring now to FIG. 2, a cross section of a part of a typical SRAM cell is shown. The cross section illustrates a common source 74 between two transistors 90 and 82. In this case, the transistors are n-channel devices formed in a p-well 70. An alpha particle 98 strikes the integrated circuit. In the p-well region 70, the energy of the particle passing through causes the generation of charge carriers. The negative charge is attracted to the neighboring n-well region 72 while positive charge is attracted to the common source 94.
It is important to note that charge storage on nodes ST1 and ST2 of the 6T SRAM cell is governed by the equation Q=C×V, where Q is the charged stored, C is the capacitance of the storage node, and V is the voltage of the node. As the power supply voltage VCC is reduced, the stored charge on the storage nodes ST1 and ST2 is reduced proportionally. If the charge generated by alpha particle penetration (Qα) exceeds the charge stored (QST), then the bi-stable flip-flop may flip states and generate a bit error. In addition, the charge on ST1 and the charge on ST2 are shared onto the BLB and BL buses, respectively, during a READ operation. If ST1 and ST2 have insufficient available charge, due to a low supply voltage perhaps coupled with alpha particle penetration, then the bit line buses will not be charged to proper levels during the READ operation and soft errors will result. It is found, therefore, that very low power supply SRAM cells can exhibit unacceptable soft error rate values.
Several prior art inventions relate to SRAM structures. U.S. Pat. No. 5,547,892 to Wuu et al describes a SRAM with a 6 transistor structure. U.S. Pat. No. 6,140,684 to Chan et al and U.S. Pat. No. 6,271,063 to Chan et al disclose a 6T SRAM formed using two thin-film transistors, two bulk transistors, and two pass transistors. U.S. Pat. No. 5,496,756 to Sharma et al teaches a nonvolatile cell comprising a 6T SRAM structure and a 3T nonvolatile structure.